Nonlinear, decentralized processing unit and related systems or methodologies

ABSTRACT

Disclosed is a processor chip that includes on-chip and off-chip software. The chip is optimized for hyperdimensional, fixed-point vector algebra to efficiently store, process, and retrieve information. A specialized on-chip data-embedding algorithm uses algebraic logic gates to convert off-chip normal data, such as images and spreadsheets, into discrete, abstract vector space where information is processed with off-chip software and on-chip accelerated computation via a desaturation method. Information is retrieved using an on-chip optimized decoding algorithm. Additional software provides an interface between a CPU and the processor chip to manage information processing instructions for efficient data transfer on- and off-chip in addition to providing intelligent processing that associates input information to allow for suggestive outputs.

CROSS-REFERENCE TO RELATED APPLICATIONS

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STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

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THE NAMES OF THE PARTIES TO A JOINT RESEARCH AGREEMENT

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REFERENCE TO AN APPENDIX SUBMITTED ON A COMPACT DISC AND INCORPORATED BYREFERENCE OF THE MATERIAL ON THE COMPACT DISC

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STATEMENT REGARDING PRIOR DISCLOSURES BY THE INVENTOR OR A JOINTINVENTOR

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BACKGROUND OF THE INVENTION Field of Invention

The subject matter of this document is related to a system and method oflarge-scale information processing in computer systems. Specifically,this subject matter pertains to encoding, processing, and decodinginformation in such a way that intelligently processes information.

Background of the Invention

Information and intelligent data processing are commonly performed by agraphics processing unit (“GPU”), which separates information, or data,into vectors which are manipulated by arithmetic logic operators inparallel. GPUs have been widely adopted over central processing units(“CPUs”) using parallel processing for the additional speed GPUsprovide. While a CPU is more often used in large-scale computing, a GPUhas the added benefit of processing more data at once, using fewercomputational resources. However, in large-scale information processing,the GPU is not often used because it does not have on-board memory tostore data, it requires vastly different software approaches to handlingthe information than what most data centers currently use, and its logicgates use arithmetic designed for floating point operations which arenot always the type of operations needed in large-scale processing. Inlarge-scale computing, the current approach is generally to employ theCPU with some specialized GPU processing. Because of this, in servercomputing applications where many CPUs and GPUs work together, such ascloud computing, computational cost concerns have become increasinglyimportant as large-scale data processing usage continues to increase.

Furthermore, intelligent computing, such as artificial intelligence(“AI”), is often computed on GPU hardware. In AI systems, the“intelligence” is simply algorithms that instruct the hardware to runcomputations; a GPU does not have intelligence to process informationbeyond its ability to run parallel processing and design specificationswith fidelity. Essentially, a GPU is unable to process informationintelligently without specific algorithms that instruct the GPU's logicgate structure to provide intelligent output. The GPU itself does notproduce intelligent computation; an unoptimized code program could use aGPU with the same inefficiency as a CPU.

Emerging intelligent information processing systems use a similarmethodology. An intelligence processing unit (“IPU”) is similar to aGPU, although the IPU's hardware is optimized specifically forbackpropagation-like algorithms, such as those used for training neuralnetworks. Neuromorphic computing is hardware optimized directly for anintelligent algorithm but is not generalized to perform large-scalenon-intelligent information processing, such as data-sharding.Additionally, edge-computing is specifically designed for a particularinput processing type with a specific desired output; the hardware hasbeen optimized directly for a single task. These applications each haveadvantages and disadvantages in computational speed, memory, and powerusage, although they need to rely on the hardware for directlyimplementing intelligent abilities and none are applicable to genericlarge-scale information processing that can adapt to differentinformation input-output pipelines.

In large-scale data processing today, data-sharding is a commontechnique to leverage multiple computer resources to process a databasethat a single computer process alone could not handle. Data-shardingworks by separating information vectors into multiple pieces of datathat are then processed on multiple different hardware components, suchas GPUs and CPUs, in parallel across computers and within each device.Although data-sharding is commonly used across many applications, itrelies on adding more computational resources without reconsidering anymathematical principles currently employed by the hardware's logicgates.

Similarly, many AI programs often use backpropagation-based methods. Inthose backpropagation-based methods, parallel processing of GPU and IPUhardware computes and accelerates a gradient, because multiple partialderivatives can be computed for gradient optimization used duringbackpropagation in parallel. However, the gradient must be trained onspecific input types, which incurs extra computational requirements asthe need for new inputs increases over time. In other words, AI programsusing backpropagation must rely more and more on parallel processing asthe amount of information increases over time. Additional reliance onparallel processing continuously requires more hardware or time spent onthe same hardware, either of which increases both computational cost andenergy consumption, limiting the economic and environmental feasibilityof long-term use.

Although some prior art in this area exists, it does not specificallyaddress the issue at hand. Prior art that relates to the methodology andsystem disclosed in this application include mathematical approachesthat leverage high-dimensional vector fields to mix information soinformation vectors can be computed in bulk. Jaeckel, U.S. Pat. No.5,113,507, uses a similar fundamental mathematical theory to usehigh-dimensional computing for vectors to use “bind” and “bundle”operations to compute integrated information vectors. Although Jaeckeldescribes the programming methodology, it does not describe how theprogram can be adapted generically to large-scale computing to multipleinput types in accelerated hardware that leverages advancements in logicgate operations and hardware designs. Overall, Jaeckel describes asystem of addressing associative memory, rather than large-scaleinformation storage, processing, and retrieval as disclosed by thisinvention.

In view of the foregoing, a need exists for a computer processing chipthat utilizes advanced mathematics to intelligently encode informationdirectly in hardware gates for large-scale, generic informationprocessing at high speeds with relatively low energy consumption.

SUMMARY OF THE INVENTION

In view of the foregoing, an object of this specification is to disclosean apparatus and related methods for processing large datasets andinformation while enabling low-power consumption and generic informationstorage, processing, retrieval, and activation with intelligentsuggestion and contextual reference. Embodiments of the discloseddevices enable users to store information with hardware optimized forlow power consumption and computational speed by reducing computationtime and memory. There are many approaches for leveraging themathematical foundations of high-dimensional computing. Described beloware several embodiments that enable appropriate approaches to allowmultiple information processing procedures that can be optimized incurrent hardware architectures.

The underlying approach of high-dimensional computing is to encodevectors into large dimensional fields. Once the vectors are in a largedimensional field, they can be computed simultaneously in mixed form,rather than individually in parallel. Many techniques can be used toencode vectors into a large dimensional field. However, embodiments ofthis invention require use of a technique that embeds the data,regardless of type, into a large binary vector to be agnostic to thetype of data being encoded. To embed the data, the embedding algorithmis used generally across all incoming data that is to be stored with thealready stored data and is then converted into a large binary vectorformat. The methods of embedding are vast. It is important to optimizeembedding for general applicability and for memory usage, speed, anddata loss fidelity. Several low-level programming languages can convertthe embedding algorithm into logic gates. The most common programminglanguage is C, which directly compiles program instruction sets intohardware operation. The underlying mathematical logic for encodingnatural information, including images, text, and numerical data, willhave a large impact on downstream information processing modules.Therefore, the embodiment's embedding module plays a crucial role inlater information processing and retrieval.

Once the information is encoded from the sensory capture unit, or CPUdirection, the information needs to be processed so it can bemanipulated according to the operator's instructions. These instructionsdictate the type of processing needed, whether it be storage andretrieval, further mathematical manipulation, or intelligent processingpipelines. A relationship within the information being processed iscreated by a module, or sub-program. Furthermore, processed informationhas a structural and temporal relationship with other environmentalinformation. For example, if a baseball is seen just before a baseballbat, the baseball and baseball bat likely have a meaningfulrepresentation in relation to the baseball. In standard informationprocessing, a temporal relationship is difficult to capture withoutproviding the software many examples of the two occurring in temporalsuccession. In intelligent information processing as described here, thetwo should be encoded and processed with some meaningful relationshipupon first instance. This encoding can be directly optimized inhardware. Similarly, in data processing that does not require encodingrelationships, the process of storing information in such a way that canbe manipulated such that a meaningful output is returned, the originaldata must be preserved such that the original data is not lost.Information theory is used to minimize data loss when processing datathat requires encoding relationships. Core processing algorithms can bewritten directly in the hardware which allows further processing tomanipulate on-chip computations. Hardware optimization here relies ondirect logic gate computations to create associations between datapoints and efficient encoding-retrieval schemes.

The encoded and processed data then needs to be retrieved off-chip forthe rest of the hardware system to use it. This output must be decodedfrom the high-dimensional mathematical form. The decoding algorithm isdirectly tied to embedding and processing methods so that once theinformation is encoded and processed it cannot lose the originalrelationships in the dataset. Therefore, decoding needs to be losslessfor pure information storage and retrieval and nearly lossless for mostintelligent processing. In advanced intelligent information processing,some loss is accepted, such as when it occurs in biologicalintelligence, so that the system can process information related to sometemporal dimension that allows suggestive information to be contextuallydriven and adaptable to novel information context.

In addition to information encoding, processing, and decoding, theunderlying mathematics used in the embodiments creates a new challenge,referred to as desaturation. As information vectors become mixed, thevalue contained in each dimension increases. Traditionally, these valuesrequire increases in memory resources, which ultimately leads toincreases in computational costs and carbon emissions. To account forthis, and reduce computational resources, a desaturation method can beused to reduce the value in each of the vector's dimensions. Ultimately,this technique increases the system's longevity to perform intelligentinformation processing within resource constraints. In practice,desaturation can be performed in many ways and desaturation methodsshould be hardware-optimized for computational resource efficiency. Whenrelying on computation methods that keep the numerical values in eachdimension of the large vector low, after binding and bundling, thevector should release information for distant temporal events. Releasinginformation for distant temporal events incurs a recent temporal eventinformation processing constraint. Further metrics enforce an“importance” metric that preserves informational relationships that areimperative to the dataset. As a standard, these desaturationcomputations should be optimized in hardware generically, largelyindependent of tasks and information input and output types.

From a high-level view, there are four important algorithms foroptimizing information storage, processing, and retrieval: embedding,processing, desaturation, and retrieval. Ideally, the algorithms shouldoccur in the above order when necessary. In one embodiment, the hardwarecan further optimize these algorithms not only in direct logic gatecomputation, but also in the data processing pipeline implementation.Computations, or algorithmic operations, can be performed in parallel.While parallelization is not a new technique, the idea of mixedinformation vector processing, or bulk parallel processing, combinedwith parallel implementation is novel.

Disclosed in this invention is the approach that takes a generic,data-type neutral embedding algorithm which transforms natural data,such as images, text, or numerical data, into a fixed-point, abstractvector space. An abstract vector uses mathematical computations thatexceed field algebra. These abstract operations can be performed oninformation vectors that are combined into single vectors without losinginformation relationships and enable original data reconstruction whennecessary. Therefore, this invention uses significantly lesscomputational memory and power consumption when compared to existingarchitectures.

Essentially, the ideal flow of information processing in currentarchitectures is to process information in vector format bothindependently and, when possible, in parallel. In the novel architecturedisclosed, the information processing pipeline encodes informationvectors into abstract high dimensional vector fields, where informationcan be processed either in bulk simultaneously and/or in parallel andretrieved either losslessly or with minimal loss depending on the amountof AI needed. In one embodiment, AI uses the hardware-optimizedalgorithms' suggestive properties directly to suggest pertinentinformation according to current context and data points' novelrelationships, or information vectors, for later contextual inference.Data storage and retrieval is either lossless data encoding andretrieval or intelligent data encoding and retrieval. In losslessencoding and retrieval, data is encoded and retrieved so that the data'sretrieval does not degrade the properties and relationships of theoriginal dataset. The lossless process encodes, processes, and retrievesdata where the data points' relationships can be exploited to provideadditional contextual relationships. Data recovery and reconstructionare exactly what was encoded, meaning the original data is preservedentirely. In intelligent encoding and retrieval, some data loss occursbecause of the extra processing computations that provide additionalmeaningful relationships between data points. Both informationprocessing types are efficient in terms of computational energy used,speed, and memory in a manner that available hardware is unable tocapture.

The present application discloses four novel mathematical algorithms toprovide the disclosed embodiments' approaches to information processing.In doing so, the disclosed program is directly implemented in hardware.The result is an improved hardware architecture and code program thatimproves energy consumption, speed, and memory over available prior art.The disclosed embodiments reduce data-sharding and increase intelligentprocessing, such as AI, while drastically reducing the need forcomputational resources. The disclosed embodiments encode datasimultaneously and in parallel while requiring significantly fewercomputational resources.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

Other objectives of the disclosure will become apparent to those skilledin the art once the invention has been shown and described. The mannerin which these objectives and other desirable characteristics can beobtained is explained in the following description and attached figuresin which:

FIG. 1 depicts a flow diagram of information storage, processing, andretrieval as separated into software and hardware stages.

FIG. 2 depicts a flow diagram of information processing instructions tomove information to a processor chip.

FIG. 3 depicts a flow diagram of information embedding, encoding, andstorage on a processor chip.

FIG. 4 depicts a flow diagram of an information desaturation process.

FIG. 5 depicts a flow diagram of an embodiment of intelligent processingsoftware.

FIG. 6 depicts a flow diagram of an on-chip decoding software.

FIG. 7 depicts a flow diagram of inter-chip operability whereinformation is jointly processed between chips.

FIG. 8 depicts a flow diagram of a preferable embodiment of the presentinvention.

It is to be noted, however, that the appended figures illustrate onlytypical embodiments of this invention and are therefore not to beconsidered limiting of its scope, for the invention may admit to otherequally effective embodiments that will be appreciated by thosereasonably skilled in the relevant arts. Also, figures are notnecessarily made to scale but are representative.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Disclosed is a processor chip and system for resource-conservativeinformation processing with accelerated hardware using hyperdimensional,fixed-point vector algebra. The system uses the improved processor chipwith a traditional computer system, including, but not limited to, inputdevices such as a mouse and keyboard; main memory; random access memory(RAM); additional processors; at least one motherboard; and a computersystem software. FIG. 1 illustrates an information processing (10) flowas separated into software and hardware stages where information comesinto the host computer via sensory captures or other storage locationson or off the host device. An on-chip embedding module (20) then movesdata on-chip. Once the data is on-chip, a process module (70)manipulates the data according to information processing (40)instructions (41). If necessary, an on-chip desaturation (30) protocolcan be employed. Once the data is processed, an on-chip decoding module(50) retrieves the data. If intelligent information processing (40) isspecified by the process flow program, an intelligence module isemployed in tandem with the decoding module. Data can be moved on-chipor off-chip during any point and can be shared between processors givenan appropriate motherboard configuration. Each on-chip module can be runin parallel on multiple processing cores.

FIG. 2 illustrates a process flow module (10) which proves informationprocessing instructions to move information to a preferred embodiment ofa processor chip. FIG. 2 defines the process flow needed for desiredoutput, where different outputs have different processing requirements(11). The processing requirements have different chip modes in apreferable embodiment of the on-chip software. The process flow moduleinstructs a CPU to send the chip to an appropriate on-chip pipelineaccording to input/output triggers. Preferably, an instruction set iscompiled into a host machine's CPU with the C programming language. Theinstruction set is a regular code file that provides an overall input tooutput (12) program to be computed. Preferably, a process type is set toinclude which data receives intelligent processing. The program candescribe an output-type instance to determine specific encoding anddecoding protocols to be performed in a decoding module. The processtype and output type then set a trigger (13) to initiate an on-chipprotocol. The on-chip protocol is a separate set of instructions thatinterfaces between the host process flow program and the chip, typicallyreferred to as a chip's compiler driver. The driver then initiates atransfer (14) through direct memory access (“DMA”). The protocol thendeploys an embedding trigger (15) to start the embedding (20) module.

FIG. 3 illustrates on-chip information embedding (20), on-chip encoding(23), and storage (24) on a preferable embodiment of a processor chip.The on-chip information embedding (20) module and process move bit datafrom another processor or primary or secondary memory source including,but not limited to, a CPU, storage, or RAM, to the processor chip. Thedata from the other memory source is the project data (21). In apreferred embodiment of the processor chip, the type of embedding modeis set based on the configuration of the information pipeline, althoughin alternate embodiments the embedding module may be variable dependingon the information pipeline's configuration. Automatic on-chip softwareprocessing transforms off-chip data to on-chip data so that informationis stored within the processor chip by employing directly optimizedlogic gates of the embedding function.

To complete the DMA, which moves data onto the chip, the on-chipembedding (20) module takes natural data and projects it intofixed-point vectors of 8192 dimensions. To compute the projection, aprior dictionary of permutations is calculated and stored in a kernel onthe chip. Together the kernel and the on-chip information encoding (23)module use a projection algorithm to encode the data in parallel intothe appropriate number of integer vectors, which is always less than thetotal number of natural information vectors. The projection uses arandom number generator such that the fixed-point vectors are encrypted.Bundle and Bind operations are used to compress multiple fixed-pointvectors into binary, or bit, vectors. A sorting algorithm is used intandem with stored priors (22) to store (24) the resultant vectors sothat encoded data is maximally distant in a high-dimensional vectorspace. The process occurs in several on-chip processors.

FIG. 4 illustrates an on-chip desaturation (30) module and an on-chipinformation desaturation process which cleans data to keep memory sizelow. In a preferable embodiment the process triggers (31) automaticallyduring embedding and processing stages, although in alternativeembodiments could trigger during different stages of chip processes.When the desaturation module automatically triggers (32) and deploys aseparate on-chip kernel periodically checks global memory and cache forfixed-point vectors which exceed memory thresholds (33). The memorythreshold checks occur when the number in each dimension has grown largeenough that its conversion to binary representation exceeds a predefinedpercentage of a fixed-point vector's memory size. Once desaturationtriggers, the appropriate stored priors are retrieved and the vector tobe desaturated is located and pulled (34) into the desaturate memorycache. The desaturation algorithm then uses the priors as instructionsfor which dimensions to reduce (35) to a predetermined smaller state.The modified fixed-point vector is then sent back to storage to continueprocessing (36). The preferable embodiment of the desaturation moduleruns in parallel with other on-chip operations and can be deployed onmultiple chips at once.

FIG. 5 illustrates a preferable embodiment of an intelligent processing(40) module and software that deploy according to a process flowprogram. The preferable embodiment of the process recruits a combinationof on-chip and off-chip software and occurs during the encoding stage(23). The intelligent processing (40) software can afford on-chipassociation according to the processing module pipeline, with furtheroff-chip instructions potentially manipulating on-chip data to providemethods for generalization and a-priori contextual suggestions (41).

A preferable embodiment of intelligent retrieval uses an informationactivation (48) software to extract special associative properties offixed-point vectors using mathematical properties of the maximallydistant fixed-point vectors (42). The association algorithm relies onlogic operations directly encoded on-chip. The intelligence is builtinto the chip and only requires instructing the chip to initiate thebuilt-in protocol to locate the necessary data (43). In alternateembodiments, other intelligent algorithms can be employed at this stagefor further integrated processing features. When other intelligentalgorithms are employed, advanced cognitive algorithms use specializedmathematics to monitor when information has been associated (45)together and store the record on-chip in the form of fixed-pointvectors.

Depending on when the associations (45) are made, links between vectors(44) are established in a record. In a preferable embodiment, the recordis then used to efficiently sequester vectors that should be active inglobal memory. Sequestering vectors allows suggestions to be made tocomplete subsets of data when only a partial subset of the data isavailable. The sequestering technique can be further extended by usingoff-chip algorithms to extend the bootstrapping (46) of contextualinformation in novel events. Additionally, the same records used forbootstrapping can also be used for generalization (47), whererelationships between input and output are learned and then inferred.The learning and inferring works by the information activation softwaresequestering vectors that should be involved in the process flowinstructions, so the instruction set must be modified less frequentlyover the information processing system's continual use. The new data isadded to the information processing pipeline, where an input-outputrelationship can be inferred by a generalization algorithm instead ofbeing directly hard-coded into the chip by host CPU instructions such asthe information processing (10) instructions. In a preferred embodimentthe next step is activating sequestered vectors (48) using aninformation activation software by pushing them to a global memory. Theactivation module is cyclical, so the record needs to be updatedcontinuously. Intelligence modules can run in parallel on-chip kernelsand use other motherboard processors to employ other intelligencealgorithms. Near the end of the intelligent retrieval processes, someintelligent processing may manipulate the data directly, which thenreplaces or becomes stored (49) in the appropriate module's globalmemory.

FIG. 6 illustrates an on-chip decoding (50) software and decoding (50)module where information vectors are projected back to their originalform or desired output form and moved off-chip by CPU instructions. Datathat has been requested (51) to be moved off-chip either by the processflow program, intelligence module, or inter-chip operability trigger thedecoding module. The preferable first step in a decoding module is thatthe decoding software automatically selects data vectors to decode,where a trigger is set (52) to remove those vectors from the rest of themodules (53). After the selected vectors are pulled into a decodingmodule's memory cache, the data is projected out (54) of highdimensional vector space, using a decoding algorithm that reassemblesthe fixed-point vectors, into bit vectors of original data form. Thedecoding algorithm completes the off-chip DMA process (55). The decodingmodule has special logic gate operations directly encoded on-chip toaccelerate the decoding algorithm.

FIG. 7 illustrates inter-chip operability (60) where information isjointly processed between processor chips and memory modules.Preferably, inter-chip operability (60) allows data to move betweenprocessors on the motherboard for joint processing after the instructedsend or share (61) trigger (62) is activated. In a preferred embodiment,at any point (63) information can be jointly processed between one ormore chips (64). The joint processing occurs by translocation betweenchips or by memory-sharing, such as with a shared cache (65), accordingto joint chip specifications and instruction sets.

FIG. 8 illustrates the scope of a preferred embodiment of a processorchip. In a standard chip design cycle, the present invention encompassesa system specification, architectural design, function design, and logicgate design in addition to software design that may be used on acompleted accelerator.

Although the method and apparatus are described above in terms ofvarious exemplary embodiments and implementations, it should beunderstood that the various features, aspects, and functionalitydescribed in one or more of the individual embodiments are not limitedin their applicability to the particular embodiment with which they aredescribed, but instead might be applied, alone or in variouscombinations, to one or more of the other embodiments of the disclosedmethod and apparatus, whether or not such embodiments are described andwhether or not such features are presented as being a part of adescribed embodiment. Thus, the breadth and scope of the claimedinvention should not be limited by any of the above-describedembodiments.

Terms and phrases used in this document, and variations thereof, unlessotherwise expressly stated, should be construed as open-ended as opposedto limiting. As examples of the foregoing: the term “including” shouldbe read as meaning “including, without limitation” or the like, the term“example” is used to provide exemplary instances of the item indiscussion, not an exhaustive or limiting list thereof, the terms “a” or“an” should be read as meaning “at least one,” “one or more,” or thelike, and adjectives such as “conventional,” “traditional,” “normal,”“standard,” “known,” and terms of similar meaning should not beconstrued as limiting the item described to a given time period or to anitem available as of a given time, but instead should be read toencompass conventional, traditional, normal, or standard technologiesthat might be available or known now or at any time in the future.Likewise, where this document refers to technologies that would beapparent or known to one of ordinary skill in the art, such technologiesencompass those apparent or known to the skilled artisan now or at anytime in the future.

The presence of broadening words and phrases such as “one or more,” “atleast,” “but not limited to,” or other like phrases in some instancesshall not be read to mean that the narrower case is intended or requiredin instances where such broadening phrases might be absent. The use ofthe term “assembly” does not imply that the components or functionalitydescribed or claimed as part of the module are all configured in acommon package. Indeed, any or all the various components of a module,whether control logic or other components, might be combined in a singlepackage or separately maintained and might further be distributed acrossmultiple locations.

Additionally, the various embodiments set forth herein are described interms of exemplary block diagrams, flow charts, and other illustrations.As will become apparent to one of ordinary skill in the art afterreading this document, the illustrated embodiments and their variousalternatives might be implemented without confinement to the illustratedexamples. For example, block diagrams and their accompanying descriptionshould not be construed as mandating a particular architecture orconfiguration.

All original claims submitted with this specification are incorporatedby reference in their entirety as if fully set forth herein.

I claim:
 1. An improved resource-conservative computer processor chipoptimized for hypergeometric, fixed-point vector algebra to store,process, and retrieve information comprising: a process flow module; aninformation embedding module; an information encoding module; aninformation desaturation module; and, an on-chip decoding module; anintelligent activation software to monitor when information has beenassociated together and stored in an on-chip record; wherein theactivation software: sequesters vectors that are active in a globalmemory; forms suggestions and generalizations of complete datasets fromavailable partial data; activates sequestered vectors by returning themto the global memory; and, updates the on-chip record continuously. 2.An improved resource-conservative computer processor chip optimized forhypergeometric, fixed-point vector algebra to store, process, andretrieve information comprising: a process flow module; an informationembedding module; an information encoding module; an informationdesaturation module; and, an on-chip decoding module; an informationdesaturation process which automatically triggers during an informationembedding and processing stage to check the dimensions of fixed-pointvectors before removing those vectors that exceed a predefinedpercentage of a fixed-point vector's memory size in order to reducevector size to a predetermined smaller state.
 3. An improvedresource-conservative computer processor chip optimized forhypergeometric, fixed-point vector algebra to store, process, andretrieve information comprising: a process flow module; an informationembedding module; an information encoding module; an informationdesaturation module; and, an on-chip decoding module; wherein theprocessor chip uses special logic gate operations to accelerate theinformation storage, processing, and retrieval an information embeddingand processing stage where the on-chip information desaturation moduleautomatically triggers to check the dimensions of fixed-point vectorsbefore removing components of the vectors which have become too large toreduce vector dimension values to a predetermined state.
 4. An improvedresource-conservative computer processor chip optimized forhypergeometric, fixed-point vector algebra to store, process, andretrieve information comprising: a process flow module; an informationembedding module; an information encoding module; an informationdesaturation module; and, an on-chip decoding module; wherein theprocessor chip uses special logic gate operations to accelerate theinformation storage, processing, and retrieval an information activationsoftware which extracts special associative properties of fixed-pointvectors to create suggestions from data subsets during an informationprocessing stage.
 5. A method for efficiently processing computer datawhile conserving resources comprising: obtaining an improvedresource-conservative computer processing chip optimized forhyperdimensional, fixed-point vector algebra comprising: a process flowmodule which uses an output-type instance to determine specific encodingand decoding protocols to be used by the improved computer processingchip before embedding the information; an on-chip information embeddingmodule which stores on-chip data that has been transformed from off-chipdata through an information embedding process and projection algorithmwhich take natural data, encrypt the data with a random numbergenerator, and project the data into fixed-point vectors of 8192dimensions; an on-chip information encoding module which uses an on-chipkernel to encode binary vectors as data in parallel to fixed-pointvectors; an on-chip information desaturation module which uses aninformation desaturation process that automatically triggers to checkthe dimensions of fixed-point vectors before removing those vectors thatexceed a predefined percentage of a vector's memory size in order toreduce vector size to a predetermined smaller state; an on-chip decodingmodule which uses a decoding software an information activation modulewhich uses an information activation software during an encoding stagewhere the activation software extracts special associative properties offixed-point vectors to create suggestions from data subsets; and, anon-chip decoding module which uses an on-chip decoding algorithm toreassemble fixed-point vectors into binary vectors of original data formto complete data transfer off-chip; installing the improved processorchip in a compatible computer system; installing required software onthe improved processor chip and computer system; and, using the improvedprocessor chip to process large amounts of data while conservingresources.